TI380C30A Datasheet, PDF (62/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
80x8x-mode bus arbitration – SIF returns control (see Figure 26)
NO.
220
223b
224b
224d
230
240
Delay time, SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH,
SRD, and SWR in the high-impedance state
Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state
Delay time, SBCLK low in cycle I2 to SOWN high
Delay time, SBCLK low in cycle I2 to SDDIR high
Delay time, SBCLK high in cycle I1 to SHRQ low
Setup time, SRD, SWR, and SBHE in the high-impedance state
before SOWN no longer low
25-MHZ
OPERATION
MIN MAX
33-MHZ
OPERATION
MIN MAX
UNIT
35
35 ns
45
0
20
27
20
45 ns
0
15 ns
22 ns
15 ns
0
0
ns
SIF Master
T3
T4
Bus Exchange
I1
I2
User Master
(T1)
(T2)
SBCLK
SHLDA
SHRQ†
SRD
SWR
SBHE
SIF
Outputs
SADH0–
SADH7
SADL0–
SADL7
SPH
SPL
SDDIR
SOWN‡
230
220
Hi-Z
240
223b
SIF
Hi-Z
220
240
SIF
Hi-Z
Write
Read
224d
224b
† _{In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it}
controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
‡ _{While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled.}
Figure 26. 80x8x-Mode Bus Arbitration – SIF Returns Control
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