TI380C30A Datasheet, PDF (25/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Table 4. User-Access Hardware Registers
80x8x 16-BIT MODE
(SI/M = 1, S8/SHALT = 0)†
WORD TRANSFERS
NORMAL MODE
SBHE = 0, SRS2 = 0
BYTE TRANSFERS
SBHE = 0, SRS2 = 1
SBHE = 1, SRS2 = 0
SRSX SRS0 SRS1
0
0
0
SIFDAT MSB
SIFDAT LSB
0
0
1
SIFDAT/INC MSB
SIFDAT/INC LSB
0
1
0
SIFADR MSB
SIFADR LSB
0
1
1
SIFCMD
SIFSTS
1
0
0
SIFACL MSB
SIFACL LSB
1
0
1
SIFADR MSB
SIFADR LSB
1
1
0
SIFADX MSB
SIFADX LSB
1
1
1
DMALEN MSB
† _{SBHE = 1 and SRS2 = 1 are not defined.}
DMALEN LSB
PSEUDO-DMA MODE ACTIVE
SBHE = 0, SRS2 = 0
SBHE = 0, SRS2 = 1
SBHE = 1, SRS2 = 0
SDMADAT MSB
DMALEN MSB
SDMAADR MSB
SDMAADX MSB
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SDMADAT LSB
DMALEN LSB
SDMAADR LSB
SDMAADX LSB
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SRSX
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SRS0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SRS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
80x8x 8-BIT MODE
(SI/M = 1, S8/SHALT = 1)
SRS2
NORMAL MODE
SBHE = X
0
SIFDAT LSB
1
SIFDAT MSB
0
SIFDAT MSB
1
SIFDAT MSB
0
SIFADR LSB
1
SIFADR MSB
0
SIFSTS
1
SIFCMD
0
SIFACL LSB
1
SIFACL MSB
0
SIFADR LSB
1
SIFADR MSB
0
SIFADX LSB
1
SIFADX MSB
0
DMALEN LSB
1
DMALEN LSB
PSEUDO-DMA MODE ACTIVE
SBHE = X
SDMADAT LSB
SDMADAT MSB
DMALEN LSB
DMALEN MSB
SDMAADR LSB
SDMAADR MSB
SDMAADX LSB
SDMAADX MSB
SIFACL LSB
SIFACL MSB
SIFACL LSB
SIFACL MSB
SIFADX LSB
SIFADX MSB
DMALEN LSB
DMALEN MSB
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
25