TI380C30A Datasheet, PDF (76/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
68xxx-mode bus arbitration – SIF returns control (see Figure 34)
NO.
220
223b
224b
224d
230
240
Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the
high-impedance state, bus release
Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state
Delay time, SBCLK low in cycle I2 to SOWN high
Delay time, SBCLK low in cycle I2 to SDDIR high
Delay time, SBCLK high to either SHRQ low or SBRQ high
Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance
state before SOWN no longer low
25-MHZ
OPERATION
MIN MAX
33-MHZ
OPERATION
MIN MAX
UNIT
35
35 ns
45
0
20
27
20
45 ns
0
15 ns
22 ns
15 ns
0
0
ns
SIF Master
T2
T3
Bus Exchange
T4
I1
User
I2
T1
SBCLK
SIF
Inputs
SBGR
SDTACK
SBRQ†
SAS
SUDS
SLDS
SIF
Outputs
SRNW
SADH0–SADH7
SADL0–SADL7
SPH
SPL
SDDIR
SOWN
230
Read
Write
SIF
Write
Read
220
240
223b
220
240
Hi-Z
Hi-Z
224d
224b
† _{In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer}
it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer
it controls.
Figure 34. 68xxx-Mode Bus Arbitration – SIF Returns Control
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