TI380C30A Datasheet, PDF (20/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
WRAP
External
Equalizer
EQ+
EQ–
XTAL
8 MHz
XT1 XT2
S4/16
ATEST
FRAQ
RCV+
RCV–
Receiver
OSC
CKT
RCV
Data
Receiver
Clock
Recovery
FRAQ
XMT+
XMT–
PHOUTA
PHOUTB
PWRDN
Transmit
Phantom
Drive
Bias Gen
Watchdog
Timer (22 ms)
Rate Error
Test Port
NABL
PXTAL
RCVR
RCLK
OSC32
REDY
DRVR+
DRVR–
WFLT
RATER
NSRT
(internal)
IREF
TDI TDO TCLK TMS TRST
Figure 2. Functional Block Diagram of the PHY
receiver
Figure 3 shows the arrangement of the line-receiver/equalizer circuit. The differential-input pair, RCV+ and
RCV–, are designed to be connected to a floating winding of an isolation transformer. Each is equipped with
a bias circuit to center the operating point of the differential input at approximately V_DD ÷ 2.
The differential-input pair consists of a pair of metal oxide semiconductor field effect transistors (MOSFETs),
each with an identical current source in its source terminal that is set to supply a nominal current of 1.5 mA. At
low signal levels, the gain of this pair is inversely proportional to the impedance connected between their
sources on EQ– and EQ+. A frequency-equalization network can be connected between EQ+ and EQ– to
provide equalization for media-signal distortion.
The internal-wrap mode is provided for self-test of the device. When selected by taking WRAP low, the normal
input path is disabled by a multiplexer and a path is enabled from the DRVR+/DRVR– input pair. Receiver gain,
thresholds, and equalization are unchanged in the internal-wrap mode.
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