TI380C30A Datasheet, PDF (8/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
MAX0
Local-memory extended-address bit. MAX0 drives AX0 at row-address time and A12 at column-address
and data-valid times for all cycles. MAX0 can be latched by MRAS. Driving A12 eases interfacing to a
burn-in address (BIA) ROM.
16
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX0
A12
A12
A12
MAX2
Local-memory extended-address bit. MAX2 drives AX2 at row-address time, which can be latched by
MRAS, and A14 at column-address and data-valid times for all cycles. Driving A14 eases interfacing to
a BIA ROM.
17
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
MAXPH
Local-memory extended address and parity — high byte. For the first quarter of a memory cycle, MAXPH
carries the extended-address bit AX1; for the second quarter of a memory cycle, MAXPH carries the
extended-address bit AX0; and for the last half of the memory cycle, MAXPH carries the parity bit for the
35
I/O ^{high data byte.}
Memory Cycle
Signal
1Q
2Q
3Q
4Q
AX1
AX0 Parity Parity
MAXPL
Local-memory extended address and parity — low byte. For the first quarter of a memory cycle, MAXPL
carries the extended-address bit AX3; for the second quarter of a memory cycle, MAXPL carries
extended-address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for the
39
I/O ^{low data byte.}
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2 Parity Parity
Local-bus clock 1 and local-bus clock 2. MBCLK1 and MBCLK2 are referenced for all local-bus transfers.
MBCLK2 lags MBCLK1 by a quarter of a cycle. MBCLK1 and MBCLK2 operate according to:
MBCLK1
MBCLK2
173
174
O
MBCLK1–
MBCLK2
8 MHz
8 MHz
12 MHz
OSCIN
64 MHz
32 MHz
48 MHz
CLKDIV
H
(4-MHz local bus)
L
(4-MHz local bus)
L
(6-MHz local bus)
MBEN
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and MADL
buses during the data phase. MBEN is used with MDDIR, which selects the buffer-output direction.
24
O
H = Buffer output disabled
L = Buffer output enabled
MBGR
37
I/O Reserved. MBGR must be left unconnected.
MBIAEN
Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM
containing the adapter’s BIA.
176
O
H = MBIAEN is driven high for any write accesses to the addresses between >00.0000 and >00.000F,
or any accesses (read/write) to any other address.
L = MBIAEN is driven low for any read from addresses between >00.0000 and >00.000F.
MBRQ
36
I/O Reserved. MBRQ must be pulled high (see Note 3)
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTE 3. Each terminal must be tied individually to VDD with a 1-kΩ pullup resistor.
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