TI380C30A Datasheet, PDF (35/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the
level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8
V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level at which
the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which typically are
1.5 ns.
2 V (high)
0.8 V (low)
test measurement
The test-load circuit shown in Figure 6 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of TI380C30A output signals.
IOL
VLOAD
Test
Point
50 pF
TTL
Output
Under
Test
Test
Point
Test
Point
50 pF
50 pF
XMT+
330Ω
XMT–
IOH
(a) TTL-OUTPUT TEST LOAD
(b) XMT+ and XMT– TEST LOAD
180 Ω
VLOAD
IEQB
EQ+
VEQW
330Ω
EQ–
(c) Iref TEST CIRCUIT
Where: VLOAD = 1.5 V, typical dc-level verification or
0.7 V, typical timing verification
(d) EQUALIZER TEST CIRCUIT
Figure 6. Test and Load Circuits
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