TI380C30A Datasheet, PDF (42/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
memory-bus timing (continued)
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns
minimum for a 6-MHz local bus).
clocks, MRAS, MCAS, and MAL to address (see Figure 12)
NO.
15 Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high
16 Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high
17 Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle
18 Pulse duration, MRAS low
19 Pulse duration, MRAS high
20
Setup time, column address (MADL0–MADL7, MAXPH, and MAXPL)
and status (MADH0–MADH7) before MCAS no longer high
21
Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL)
and status (MADH0–MADH7) after MCAS low
22
Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL)
and status (MADH0–MADH7) after MRAS no longer high
23 Pulse duration, MCAS low
24 Pulse duration, MCAS high, refresh cycle follows read or write cycle
25 Hold time, row address on MAXL0–MAXL7, MAXPH, and MAXPL after MAL low
26 Setup time, row address on MAXL0–MAXL7, MAXPH, and MAXPL before MAL no longer high
27 Pulse duration, MAL high
28 Setup time, address/enable on MAX0, MAX2, and MROMEN before MAL no longer high
29 Hold time, address/enable of MAX0, MAX2, and MROMEN after MAL low
30 Setup time, address on MADH0–MADH7 before MAL no longer high
31 Hold time, address on MADH0–MADH7 after MAL low
MIN
1.5tM–11.5
tM–6.5
8tM
4.5tM–5
3.5tM–5
0.5tM–9
MAX
UNIT
ns
ns
ns
ns
ns
ns
tM–5
ns
2.5tM–6.5
ns
3tM–9
ns
2tM–9
ns
1.5tM–9
ns
tM–9
ns
tM–9
ns
tM–9
ns
1.5tM–9
ns
tM–9
ns
1.5tM–9
ns
42
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