LAN9311 Datasheet, PDF (50/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
Bit 29 (1588_EVNT)
of INT_STS register
1588 Time Stamp Interrupt Register
1588_INT_STS_EN
Bit 28 (SWITCH_INT)
of INT_STS register
Switch Fabric Interrupt Registers
SW_IMR
SW_IPR
Bit 6 (BM)
of SW_IPR register
Buffer Manager Interrupt Registers
BM_IMR
BM_IPR
Bit 5 (SWE)
of SW_IPR register
Switch Engine Interrupt Registers
SWE_IMR
SWE_IPR
Bits [2,1,0] (MAC_[2,1,MII])
of SW_IPR register
Port [2,1,0] MAC Interrupt Registers
MAC_IMR_[2,1,MII]
MAC_IPR_[2,1,MII]
Bit 27 (PHY_INT2)
of INT_STS register
Port 2 PHY Interrupt Registers
PHY_INTERRUPT_SOURCE_2
PHY_INTERRUPT_MASK_2
Bit 26 (PHY_INT1)
of INT_STS register
Port 1 PHY Interrupt Registers
PHY_INTERRUPT_SOURCE_1
PHY_INTERRUPT_MASK_1
Bit 17 (PME_INT)
of INT_STS register
Power Management Control Register
PMT_CTRL
Revision 2.0 (02-14-13)
Bit 12 (GPIO)
of INT_STS register
GPIO Interrupt Register
GPIO_INT_STS_EN
Figure 5.1 Functional Interrupt Register Hierarchy
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DATASHEET
SMSC LAN9311/LAN9311i