LAN9311 Datasheet, PDF (144/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
10.2.2.5
I²C EEPROM Byte Writes
Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I²C master finishes the write cycle with a stop condition. If the EEPROM slave fails to
send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM
Command Register (E2P_CMD) is set.
Following the data byte write cycle, the I²C master will poll the EEPROM to determine when the byte
write is finished. A start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I²C master
will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I²C
master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.
Figure 10.4 illustrates typical I²C EEPROM byte write.
Data Cycle
Poll Cycle
Poll Cycle
Poll Cycle
Conclude
... ^{Data Byte}
Control Byte
Control Byte
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
S
1
0
1
0
0
0
0
0
A
C
K
S
1
0
1
0
0
0
0
0
A
C
K
Control Byte
A
S1 0 1 0 0 0 0 0C SP
K
Chip / Block R/~W
Select Bits
Chip / Block R/~W
Select Bits
Figure 10.6 I²C EEPROM Byte Write
Chip / Block R/~W
Select Bits
For a register level description of a write operation, refer to Section 10.2.1, "EEPROM Controller
Operation," on page 139.
Revision 2.0 (02-14-13)
144
DATASHEET
SMSC LAN9311/LAN9311i