LAN9311 Datasheet, PDF (245/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

14.2.7.2
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
PHY Management Interface Access Register (PMI_ACCESS)
Offset:
0A8h
Size:
EEPROM Loader
Access Only
32 bits
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the PHY Management Interface Data
Register (PMI_DATA) to perform write operations to the PHYs.
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to
Section 10.2.4, "EEPROM Loader," on page 150 for additional information.
BITS
DESCRIPTION
31:16
15:11
10:6
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to Section 7.1.1,
"PHY Addressing," on page 82 for information on PHY address
assignments.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to Section 14.4,
"Ethernet PHY Control and Status Registers," on page 287 for detailed
descriptions on all PHY registers.
5:2 RESERVED
1
RESERVED
Note: This bit must always be written with a value of 1.
TYPE
RO
WO
WO
RO
WO
DEFAULT
-
00000b
00000b
-
0b
0
RESERVED
RO
0b
SMSC LAN9311/LAN9311i
245
DATASHEET
Revision 2.0 (02-14-13)