LAN9311 Datasheet, PDF (142/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Figure 10.2 displays the various bus states of a typical I²C cycle.
EE_SDA
data
can
change
data
stable
data
can
change
data
can
change
data
stable
data
can
change
S
Sr
P
EE_SCL
Start Condition
Data Valid
or Ack
Re-Start
Condition
Figure 10.2 I²C Cycle
Data Valid
or Ack
Stop Condition
10.2.2.2
I²C EEPROM Device Addressing
The I²C EEPROM is addressed for a read or write operation by first sending a control byte followed
by the address byte or bytes. The control byte is preceded by a start condition. The control byte and
address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command
Register (E2P_CMD) is set.
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The
control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for
address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set
low. The direction bit is set low to indicate the address is being written.
Figure 10.3 illustrates typical I²C EEPROM addressing bit order for single and double byte addressing.
Control Byte
Address Byte
S
1
0
1
0
A
1
0
A
9
A
8
0
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
Control Byte
Address High
Byte
Address Low
Byte
S
1
0
1
0
0
0
0
0
A
C
K
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
Chip / Block R/~W
Select Bits
Single Byte Addressing
Chip / Block R/~W
Select Bits
Double Byte Addressing
Figure 10.3 I²C EEPROM Addressing
10.2.2.3
I²C EEPROM Byte Read
Following the device addressing, a data byte may be read from the EEPROM by outputting a start
condition and control byte with a control code of 1010b, chip/block select bits as described in
Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then
sends a no-acknowledge, followed by a stop condition.
Revision 2.0 (02-14-13)
142
DATASHEET
SMSC LAN9311/LAN9311i