LAN9311 Datasheet, PDF (381/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
Register #:
1811h
Size:
32 bits
This register is used to read and write the DIFFSERV table. A write to this address performs the
specified access. This table is used to map the received IP ToS/CS to a priority.
For a read access, the Operation Pending bit in the Switch Engine DIFFSERV Table Command Status
Register (SWE_DIFFSERV_TBL_CMD_STS) indicates when the command is finished. The Switch
Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) can then be read.
F o r a w r i t e a c c e s s , t h e S w i t c h E n g i n e D I F F S E RV Ta b l e W r i t e D a ta R e g i s t e r
(SWE_DIFFSERV_TBL_WR_DATA) register should be written first. The Operation Pending bit in the
Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
indicates when the command is finished.
BITS
31:8
7
6
5:0
DESCRIPTION
RESERVED
DIFFSERV Table RnW
This bit specifies a read(1) or a write(0) command.
RESERVED
DIFFSERV Table Index
This field specifies the ToS/CS entry that is accessed.
TYPE
RO
R/W
RO
R/W
DEFAULT
-
0b
-
0h
SMSC LAN9311/LAN9311i
381
DATASHEET
Revision 2.0 (02-14-13)