LAN9311 Datasheet, PDF (453/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

15.5.9
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 112 for a functional
description of this mode.
FIFO_SEL
A[2:1], END_SEL
t_asu
nCS, nWR
D[15:0]
t_cycle
t_ah
t_csl
t_csh
t_dsu
t_dh
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
DESCRIPTION
MIN
TYP
Write Cycle Time
45
nCS, nWER Assertion Time
32
nCS, nWR De-assertion Time
13
Address, FIFO_SEL Setup to nCS, nWR Assertion
0
Address, FIFO_SEL Hold Time
0
Data Setup to nCS, nWR De-assertion
7
Data Hold Time
0
MAX
UNITS
nS
nS
nS
nS
nS
nS
nS
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
SMSC LAN9311/LAN9311i
453
DATASHEET
Revision 2.0 (02-14-13)