LAN9311 Datasheet, PDF (143/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Figure 10.4 illustrates typical I²C EEPROM byte read for single and double byte addressing.
Control Byte
Data Byte
A
C
K
S
1
0
1
0
A
1
0
A
9
A
8
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Control Byte
Data Byte
A
C
K
S
1
0
1
0
0
0
0
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Chip / Block R/~W
Select Bits
Single Byte Addressing Read
Chip / Block R/~W
Select Bits
Double Byte Addressing Read
Figure 10.4 I²C EEPROM Byte Read
10.2.2.4
For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller
Operation," on page 139.
I²C EEPROM Sequential Byte Reads
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting
a start condition and control byte with a control code of 1010b, chip/block select bits as described in
Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I²C master then
sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until
the last desired byte is read, at which point the I²C master sends a no-acknowledge, followed by a
stop condition.
Figure 10.4 illustrates typical I²C EEPROM sequential byte reads for single and double byte
addressing.
... ^{Control Byte}
Data Byte
Data Byte
A
C
K
S
1
0
1
0
A
1
0
A
9
A
8
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
Data Byte
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
P
K
Chip / Block R/~W
Select Bits
Single Byte Addressing Sequential Reads
Control Byte
Data Byte
Data Byte
Data Byte
... ^A
C
K
S
1
0
1
0
0
0
0
1
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
P
K
Chip / Block R/~W
Select Bits
Double Byte Addressing Sequential Reads
Figure 10.5 I²C EEPROM Sequential Byte Reads
Sequential reads are used by the EEPROM Loader. Refer to Section 10.2.4, "EEPROM Loader" for
additional information.
For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller
Operation," on page 139.
SMSC LAN9311/LAN9311i
143
DATASHEET
Revision 2.0 (02-14-13)