LAN9311 Datasheet, PDF (372/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
Register #:
1805h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Read Data 1 Register
(SWE_ALR_RD_DAT_1) to read the ALR table. It contains the first 32 bits of the ALR entry and is
loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command
Register (SWE_ALR_CMD). This register is only valid when either of the Valid or End of Table bits in
the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) are set.
BITS
31:0
DESCRIPTION
MAC Address
This field contains the first 32 bits of the ALR entry. These bits correspond
to the first 32 bits of the MAC address. Bit 0 holds the LSB of the first byte
(the multicast bit).
TYPE
RO
DEFAULT
00000000h
Revision 2.0 (02-14-13)
372
DATASHEET
SMSC LAN9311/LAN9311i