LAN9311 Datasheet, PDF (167/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 14 Register Descriptions
This section describes the various LAN9311/LAN9311i control and status registers (CSR’s). These
registers are broken into 5 categories. The following sections detail the functionality and accessibility
of all the LAN9311/LAN9311i registers within each category:
 Section 14.1, "TX/RX FIFO Ports," on page 168
 Section 14.2, "System Control and Status Registers," on page 169
 Section 14.3, "Host MAC Control and Status Registers," on page 271
 Section 14.4, "Ethernet PHY Control and Status Registers," on page 287
 Section 14.5, "Switch Fabric Control and Status Registers," on page 309
Figure 14.1 contains an overall base register memory map of the LAN9311/LAN9311i. This memory
map is not drawn to scale, and should be used for general reference only.
Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 19.
Note: Not all LAN9311/LAN9311i registers are memory mapped or directly addressable. For details
on the accessibility of the various LAN9311/LAN9311i registers, refer the register sub-sections
listed above.
3FFh
... _RESERVED
2E0h
2DCh
Switch CSR Direct Data
...
Registers
200h
1DCh
1C0h
1B0h
1ACh
19Ch
Virtual PHY Registers
Switch Interface Registers
1588 Registers
100h
0A8h _{Host MAC Interface Registers}
0A4h
050h
04Ch
048h
044h
040h
03Ch
020h
01Ch
Base + 000h
TX Status FIFO PEEK
TX Status FIFO Port
RX Status FIFO PEEK
RX Status FIFO Port
TX Data FIFO Port
& Alias Ports
RX Data FIFO Port
& Alias Ports
SMSC LAN9311/LAN9311i
Figure 14.1 LAN9311/LAN9311i Base Register Memory Map
167
DATASHEET
Revision 2.0 (02-14-13)