LAN9311 Datasheet, PDF (307/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
Index (decimal): 30
Size:
16 bits
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
BITS
15:8
7
6
5
4
3
2
1
0
DESCRIPTION
RESERVED
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
RESERVED
TYPE
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
DEFAULT
-
0b
0b
0b
0b
0b
0b
0b
-
SMSC LAN9311/LAN9311i
307
DATASHEET
Revision 2.0 (02-14-13)