LAN9311 Datasheet, PDF (298/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x)
Index (decimal): 5
Size:
16 bits
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-
Negotiation process between the link partner and the Port x PHY.
BITS
15
14
13
12
11
10
9
8
7
DESCRIPTION
Next Page
This bit indicates the link partner PHY page capability.
0: Link partner PHY does not advertise next page capability
1: Link partner PHY advertises next page capability
Acknowledge
This bit indicates whether the link code word has been received from the
partner.
0: Link code word not yet received from partner
1: Link code word received from partner
Remote Fault
This bit indicates whether a remote fault has been detected.
0: No remote fault
1: Remote fault detected
RESERVED
Asymmetric Pause
This bit indicates the link partner PHY asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner
1: Asymmetric PAUSE toward link partner
Pause
This bit indicates the link partner PHY symmetric pause capability.
0: No Symmetric PAUSE toward link partner
1: Symmetric PAUSE toward link partner
100BASE-T4
This bit indicates the link partner PHY 100BASE-T4 capability.
0: 100BASE-T4 ability not supported
1: 100BASE-T4 ability supported
100BASE-X Full Duplex
This bit indicates the link partner PHY 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not supported
1: 100BASE-X full duplex ability supported
100BASE-X Half Duplex
This bit indicates the link partner PHY 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
DEFAULT
0b
0b
0b
-
0b
0b
0b
0b
0b
Revision 2.0 (02-14-13)
298
DATASHEET
SMSC LAN9311/LAN9311i