LAN9311 Datasheet, PDF (446/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
15.5.2 Reset and Configuration Strap Timing
This diagram illustrates the nRST pin timing requirements and its relation to the configuration strap
pins and output drive. Assertion of nRST is not a requirement. However, if used, it must be asserted
for the minimum period specified. Please refer to Section 4.2, "Resets," on page 36 for additional
information.
nRST
Configuration
Strap Pins
Output Drive
t_rstia
t_css
t_csh
t_odad
Figure 15.2 nRST Reset Pin Timing
SYMBOL
t_rstia
t_css
t_csh
t_odad
Table 15.6 nRST Reset Pin Timing Values
DESCRIPTION
MIN
nRST input assertion time
200
Configuration strap pins setup to nRST deassertion
200
Configuration strap pins hold after nRST deassertion
10
Output drive after deassertion
30
TYP
MAX UNITS
μS
nS
nS
nS
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 4.2.4,
"Configuration Straps," on page 40 for details.
Revision 2.0 (02-14-13)
446
DATASHEET
SMSC LAN9311/LAN9311i