LAN9311 Datasheet, PDF (450/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
15.5.6
RX Data FIFO Direct PIO Read Cycle Timing
Please refer to Section 8.5.6, "RX Data FIFO Direct PIO Reads," on page 109 for a functional
description of this mode.
FIFO_SEL
A[x:1], END_SEL
nCS, nRD
D[15:0]
t_asu
t_csl
t_csdv
t_don
t_cycle
t_ah
t_csh
t_doff
t_doh
Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
SYMBOL
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
DESCRIPTION
MIN
TYP
Read Cycle Time
45
CS, nRD Assertion Time
32
nCS, nRD De-assertion Time
13
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
0
Address, FIFO_SEL Hold Time
0
Data Buffer Turn On Time
0
Data Buffer Turn Off Time
Data Output Hold Time
0
MAX
30
9
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle
ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Revision 2.0 (02-14-13)
450
DATASHEET
SMSC LAN9311/LAN9311i