LAN9311 Datasheet, PDF (251/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

14.2.8.3
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Virtual PHY Identification MSB Register (VPHY_ID_MSB)
Offset:
1C8h
Index (decimal): 2
Size:
32 bits
This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI).
The LSB of the Virtual PHY OUI is contained in the Virtual PHY Identification LSB Register
(VPHY_ID_LSB).
BITS
DESCRIPTION
31:16 RESERVED
(See Note 14.23)
15:0 PHY ID
This field contains the MSB of the Virtual PHY OUI (Note 14.24).
TYPE
RO
R/W
DEFAULT
-
0000h
Note 14.23 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
Note 14.24 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
SMSC LAN9311/LAN9311i
251
DATASHEET
Revision 2.0 (02-14-13)