LAN9311 Datasheet, PDF (16/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 1 Preface
1.1
General Terms
100BT
ADC
ALR
BLW
BM
BPDU
Byte
CSMA/CD
CSR
CTR
DA
DWORD
EPC
FCS
FIFO
FSM
GPIO
HBI
HBIC
Host
IGMP
Inbound
Level-Triggered Sticky Bit
lsb
LSB
MDI
MDIX
Revision 2.0 (02-14-13)
100BASE-T (100Mbps Fast Ethernet, IEEE 802.3u)
Analog-to-Digital Converter
Address Logic Resolution
Baseline Wander
Buffer Manager - Part of the switch fabric
Bridge Protocol Data Unit - Messages which carry the Spanning Tree
Protocol information
8-bits
Carrier Sense Multiple Access / Collision Detect
Control and Status Registers
Counter
Destination Address
32-bits
EEPROM Controller
Frame Check Sequence - The extra checksum characters added to the end
of an Ethernet frame, used for error detection and correction.
First In First Out buffer
Finite State Machine
General Purpose I/O
Host Bus Interface. The physical bus connecting the LAN9311/LAN9311i to
the host. Also referred to as the Host Bus.
Host Bus Interface Controller. The hardware module that interfaces
theLAN9311/LAN9311i to the HBI.
External system (Includes processor, application software, etc.)
Internet Group Management Protocol
Refers to data input to the LAN9311/LAN9311i from the host
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true, and the
status bit is cleared by writing a zero.
Least Significant Bit
Least Significant Byte
Medium Dependant Interface
Media Independent Interface with Crossover
16
DATASHEET
SMSC LAN9311/LAN9311i