LAN9311 Datasheet, PDF (449/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

15.5.5
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
PIO Burst Read Cycle Timing
Please refer to Section 8.5.5, "PIO Burst Reads," on page 108 for a functional description of this mode.
A[x:5], END_SEL
A[4:1]
nCS, nRD
D[15:0]
t_acyc
t_asu
t_csdv
t_don
t_acyc
t_adv
t_adv
t_acyc
t_ah
t_csh
t_adv
t_doff
tdoh
Figure 15.5 PIO Burst Read Cycle Timing
SYMBOL
t_csh
t_csdv
t_acyc
t_asu
t_adv
t_ah
t_don
t_doff
t_doh
Table 15.9 PIO Burst Read Cycle Timing Values
DESCRIPTION
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD Valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
13
45
0
0
0
0
MAX
30
40
9
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
Note: A[1] must toggle, fresh data is supplied each time A[1] toggles.
SMSC LAN9311/LAN9311i
449
DATASHEET
Revision 2.0 (02-14-13)