LAN9311 Datasheet, PDF (240/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
Offset:
1F4h
Size:
32 bits
This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This
register is used in conjunction with Switch Fabric MAC Address High Register
(SWITCH_MAC_ADDRH). The contents of this register are optionally loaded from the EEPROM at
power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte
(bits [31:24]) is loaded from address 04h of the EEPROM. These EEPROM values are also loaded
into the Host MAC Address Low Register (HMAC_ADDRL). The Host can update the contents of this
field after the initialization process has completed.
Refer to Section 9.6, "Host MAC Address," on page 120 for details on how the EEPROM Loader loads
this register. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for information on using the
EEPROM Loader.
BITS
31:0
DESCRIPTION
Physical Address[31:0]
This field contains the lower 32-bits (31:0) of the physical address of the
Switch Fabric MACs.
TYPE
R/W
DEFAULT
FF0F8000h
Revision 2.0 (02-14-13)
240
DATASHEET
SMSC LAN9311/LAN9311i