LAN9311 Datasheet, PDF (200/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
BITS
18
17
16
15:0
DESCRIPTION
EEPROM Loader Address Overflow (LOADER_OVERFLOW)
This bit indicates that the EEPROM Loader tried to read past the end of the
EEPROM address space. This indicates misconfigured EEPROM data.
This bit is cleared when the EEPROM Loader is restarted with a RELOAD
command, Soft Reset(SRST), or a Digital Reset(DIGITAL_RST).
EEPROM Controller Timeout (EPC_TIMEOUT)
This bit is set when a timeout occurs, indicating the last operation was
unsuccessful. If an EEPROM ERASE, ERAL, WRITE or WRAL operation is
performed and no response is received from the EEPROM within 30mS, the
EEPROM controller will timeout and return to its idle state.
For the I²C mode, the bit is also set if the EEPROM fails to respond with
the appropriate ACKs, if the EEPROM slave device holds the clock low for
more than 30ms, or if an unsupported EPC_COMMAND is attempted.
This bit is cleared when written high.
Note:
When in Microwire mode, if an EEPROM device is not connected,
an internal pull-down on the EEDI pin will keep the EEDI signal low
and allow timeouts to occur. If EEDI is pulled high externally, EPC
commands will not time out if an EEPROM device is not connected.
In this case the EPC_BUSY bit will be cleared as soon as the
command sequence is complete. It should also be noted that the
ERASE, ERAL, WRITE and WRAL commands are the only EPC
commands that will timeout if an EEPROM device is not present
AND the EEDI signal is pulled low.
Configuration Loaded (CFG_LOADED)
When set, this bit indicates that a valid EEPROM was found and the
EEPROM Loader completed normally. This bit is set upon a successful load.
It is cleared on power-up, pin and DIGITAL_RST resets, Soft Reset(SRST),
or at the start of a RELOAD.
This bit is cleared when written high.
EEPROM Controller Address (EPC_ADDRESS)
This field is used by the EEPROM Controller to address a specific memory
location in the serial EEPROM. This address must be byte aligned.
TYPE
RO
R/WC
R/WC
R/W
DEFAULT
0b
0b
0b
0000h
Revision 2.0 (02-14-13)
200
DATASHEET
SMSC LAN9311/LAN9311i