LAN9311 Datasheet, PDF (34/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
PIN
77-79,
82
63
71
NAME
General
Purpose I/O
Data
Interrupt
Output
System Reset
Input
Table 3.7 Miscellaneous Pins
SYMBOL
BUFFER
TYPE
DESCRIPTION
GPIO[11:8]
IRQ
nRST
IS/OD12/
O12
(PU)
Note 3.7
General Purpose I/O Data: These general
purpose signals are fully programmable as either
push-pull outputs, open-drain outputs, or Schmitt-
triggered inputs by writing the General Purpose I/O
Configuration Register (GPIO_CFG) and General
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Chapter 13, "GPIO/LED Controller," on page 163.
Note:
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in Table 3.1 and Table 3.2.
O8/OD8
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the Interrupt Configuration
Register (IRQ_CFG). For more information, refer to
Chapter 5, "System Interrupts," on page 49.
IS
(PU)
System Reset Input: This active low signal allows
external hardware to reset the LAN9311/LAN9311i.
The LAN9311/LAN9311i also contains an internal
power-on reset circuit. Thus, this signal may be left
unconnected if an external hardware reset is not
needed. When used, this signal must adhere to the
reset timing requirements as detailed in Section
15.5.2, "Reset and Configuration Strap Timing," on
page 446.
Note:
The LAN9311/LAN9311i must always be
read at least once after power-up or reset
to ensure that write operations function
properly.
Test 1
TEST1
AI
Test 1: This pin must be tied to VDD33IO for
75
proper operation.
Test 2
TEST2
AI
Test 2: This pin must be tied to VDD33IO for
108
proper operation.
Power
Management
Event
62
PME
O8/OD8
Power Management Event: When programmed
accordingly, this signal is asserted upon detection
of a wakeup event. The polarity and buffer type of
this signal is programmable via the PME_EN bit of
the Power Management Control Register
(PMT_CTRL).
Refer to Chapter 4, "Clocking, Resets, and Power
Management," on page 36 for additional
information on the LAN9311/LAN9311i power
management features.
Note 3.7 The input buffers are enabled when configured as GPIO inputs only.
Revision 2.0 (02-14-13)
34
DATASHEET
SMSC LAN9311/LAN9311i