LAN9311 Datasheet, PDF (178/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.2.1.3 Interrupt Enable Register (INT_EN)
Offset:
05Ch
Size:
32 bits
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables
the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register (with the exception of SW_INT_EN). For descriptions of each interrupt, refer
to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register.
BITS
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
DESCRIPTION
Software Interrupt Enable (SW_INT_EN)
Device Ready Enable (READY_EN)
1588 Interrupt Event Enable (1588_EVNT_EN)
Switch Engine Interrupt Event Enable (SWITCH_INT_EN)
Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)
Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN)
RESERVED
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt Enable (RXD_INT_EN)
GP Timer Interrupt Enable (GPT_INT_EN)
RESERVED
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow Interrupt Enable (TXSO_EN)
Receive Watchdog Time-out Interrupt Enable (RWT_INT_EN)
Receiver Error Interrupt Enable (RXE_INT_EN)
Transmitter Error Interrupt Enable (TXE_INT_EN)
GPIO Interrupt Event Enable (GPIO_EN)
RESERVED - This bit must be written with 0b for proper operation.
TX Data FIFO Overrun Interrupt Enable (TDFO_EN)
TX Data FIFO Available Interrupt Enable (TDFA_EN)
TX Status FIFO Full Interrupt Enable (TSFF_EN)
TX Status FIFO Level Interrupt Enable (TSFL_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
-
0b
0b
0b
-
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Revision 2.0 (02-14-13)
178
DATASHEET
SMSC LAN9311/LAN9311i