LAN9311 Datasheet, PDF (448/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
15.5.4 PIO Read Cycle Timing
Please refer to Section 8.5.4, "PIO Reads," on page 107 for a functional description of this mode.
A[x:1], END_SEL
nCS, nRD
D[15:0]
t_asu
t_csl
t_csdv
t_don
t_cycle
t_ah
t_csh
t_doff
t_doh
Figure 15.4 PIO Read Cycle Timing
SYMBOL
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
Table 15.8 PIO Read Cycle Timing Values
DESCRIPTION
MIN
Read Cycle Time
45
nCS, nRD Assertion Time
32
nCS, nRD De-assertion Time
13
nCS, nRD Valid to Data Valid
Address setup to nCS, nRD Valid
0
Address Hold Time
0
Data Buffer Turn On Time
0
Data Buffer Turn Off Time
Data Output Hold Time
0
TYP
MAX UNITS
nS
nS
nS
30
nS
nS
nS
nS
9
nS
nS
Note: A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted
in any order.
Revision 2.0 (02-14-13)
448
DATASHEET
SMSC LAN9311/LAN9311i