LAN9311 Datasheet, PDF (295/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

14.4.2.5
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
Index (decimal): 4
Size:
16 bits
This read/write register contains the advertised ability of the Port x PHY and is used in the Auto-
Negotiation process with the link partner.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
command. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for additional information.
BITS
DESCRIPTION
15:14 RESERVED
13 Remote Fault
This bit determines if remote fault indication will be advertised to the link
partner.
0: Remote fault indication not advertised
1: Remote fault indication advertised
12 RESERVED
Note: This bit should be written as 0.
11 Asymmetric Pause
This bit determines the advertised asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner advertised
1: Asymmetric PAUSE toward link partner advertised
10 Symmetric Pause
This bit determines the advertised symmetric pause capability.
0: No Symmetric PAUSE toward link partner advertised
1: Symmetric PAUSE toward link partner advertised
9
RESERVED
8
100BASE-X Full Duplex
This bit determines the advertised 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not advertised
1: 100BASE-X full duplex ability advertised
7
100BASE-X Half Duplex
This bit determines the advertised 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not advertised
1: 100BASE-X half duplex ability advertised
6
10BASE-T Full Duplex
This bit determines the advertised 10BASE-T full duplex capability.
0: 10BASE-T full duplex ability not advertised
1: 10BASE-T full duplex ability advertised
TYPE
RO
R/W
DEFAULT
-
0b
R/W
0b
R/W
0b
Note 14.53
R/W
Note 14.53
Note 14.54
RO
-
R/W
1b
R/W
1b
R/W
Note 14.55
Table 14.8
SMSC LAN9311/LAN9311i
295
DATASHEET
Revision 2.0 (02-14-13)