LAN9311 Datasheet, PDF (260/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.2.9 Miscellaneous
This section details the remainder of the System CSR’s. These registers allow for monitoring and
configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing,
power management, hardware configuration, general purpose timer, and free running counter.
14.2.9.1 Chip ID and Revision (ID_REV)
Offset:
050h
Size:
32 bits
This read-only register contains the ID and Revision fields for the LAN9311/LAN9311i.
BITS
DESCRIPTION
31:16 Chip ID
This field indicates the chip ID.
15:0 Chip Revision
This field indicates the design revision.
Note 14.46 Default value is dependent on device revision.
TYPE
RO
RO
DEFAULT
9311h
Note 14.46
Revision 2.0 (02-14-13)
260
DATASHEET
SMSC LAN9311/LAN9311i