LAN9311 Datasheet, PDF (452/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
15.5.8
PIO Write Cycle Timing
Please refer to Section 8.5.8, "PIO Writes," on page 111 for a functional description of this mode.
A[x:1], END_SEL
nCS, nWR
D[15:0]
t_asu
t_cycle
t_ah
t_csl
t_csh
t_dsu
t_dh
Figure 15.8 PIO Write Cycle Timing
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
Table 15.12 PIO Write Cycle Timing Values
DESCRIPTION
MIN
Write Cycle Time
45
nCS, nWR Assertion Time
32
nCS, nWR De-assertion Time
13
Address Setup to nCS, nWR Assertion
0
Address Hold Time
0
Data Setup to nCS, nWR De-assertion
7
Data Hold Time
0
TYP
MAX UNITS
nS
nS
nS
nS
nS
nS
nS
Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any
order.
Revision 2.0 (02-14-13)
452
DATASHEET
SMSC LAN9311/LAN9311i