LAN9311 Datasheet, PDF (461/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 17.1 Customer Revision History (continued)
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.5 (10-28-08)
Rev. 1.3 (07-03-08)
Section 14.2.4.1, "EEPROM
Command Register
(E2P_CMD)," on page 198
Corrected CFG_LOADED bit type from “RO” to
“R/WC”
Section 15.6, "Clock
Circuit," on page 455
Changed max ESR value from 30 to 50 Ohms and
corrected typos in operating temerpature range.
All
Fixed various typos
Port x PHY Special
Control/Status Register
(PHY_SPECIAL_CONTROL
_STATUS_x) on page 308
Updated RESERVED bits 11:5 definition to
“RESERVED - Write as 0000010b, ignore on
read”, changed default to 0000010b, and made
field R/W.
Wake-Up Frame Detection
section of Host MAC
Chapter and MAC_CR
register description
Added note at end of WUFF section and to the
BCAST bit of the MAC_CR register stating:
When wake-up frame detection is enabled via the
WUEN bit of the HMAC_WUCSR register, a
broadcast wake-up frame will wake-up the device
despite the state of the Disable Broadcast Frames
(BCAST) bit in the HMAC_CR register.
HMAC_WUCSR register
Fixed error in GUE bit description: “....the MAC
Address [1:0] bits...” changed to “...the MAC
Address [0] bits....”.
Port x PHY Auto-Negotiation
Advertisement Register
(PHY_AN_ADV_x) on page
295
Bits 15 and 9 made RESERVED.
Section 15.6, "Clock
Circuit," on page 455
Changed minimum drive level from 0.5mW to
300uW
SMSC LAN9311/LAN9311i
461
DATASHEET
Revision 2.0 (02-14-13)