LAN9311 Datasheet, PDF (390/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
Register #:
1845h
Size:
32 bits
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
BITS
DESCRIPTION
31:16
15:14
RESERVED
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 7.
13:12
Priority 6 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 6.
11:10
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 5.
9:8 Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 4.
7:6 Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 3.
5:4 Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 2.
3:2 Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 1.
1:0 Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 0.
TYPE
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
-
11b
11b
10b
10b
01b
00b
00b
01b
Revision 2.0 (02-14-13)
390
DATASHEET
SMSC LAN9311/LAN9311i