LAN9311 Datasheet, PDF (103/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 8.1 Read After Write Timing Rules
REGISTER NAME
RX Data FIFO
RX Status FIFO
RX Status FIFO PEEK
TX Status FIFO
TX Status FIFO PEEK
ID_REV
IRQ_CFG
INT_STS
INT_EN
BYTE_TEST
FIFO_INT
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPT_CFG
GPT_CNT
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
AFC_CFG
1588_CLOCK_HI_RX_CAPTURE_1
1588_CLOCK_LO_RX_CAPTURE_1
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1
1588_SRC_UUID_LO_RX_CAPTURE_1
1588_CLOCK_HI_TX_CAPTURE_1
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
0
0
0
0
0
0
135
90
45
0
45
45
45
45
45
0
135
315
45
135
180
0
45
45
45
0
0
0
0
0
NUMBER OF BYTE_TEST
READS
(ASSUMING T_CYC OF 45NS)
0
0
0
0
0
0
3
2
1
0
1
1
1
1
1
0
3
7
1
3
4
0
1
1
1
0
0
0
0
0
SMSC LAN9311/LAN9311i
103
DATASHEET
Revision 2.0 (02-14-13)