LAN9311 Datasheet, PDF (451/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

15.5.7
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
RX Data FIFO Direct PIO Burst Read Cycle Timing
Please refer to Section 8.5.7, "RX Data FIFO Direct PIO Burst Reads," on page 110 for a functional
description of this mode.
FIFO_SEL
END_SEL
A[2:1]
nCS, nRD
D[15:0]
t_acyc
t_asu
t_csdv
t_don
t_acyc
t_adv
t_adv
t_acyc
t_ah
t_csh
t_adv
t_doff
t_doh
Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL
t_csh
t_csdv
t_acyc
t_asu
t_adv
t_ah
t_don
t_doff
t_doh
Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values
DESCRIPTION
MIN
TYP
MAX
nCS, nRD De-assertion Time
13
nCS, nRD Valid to Data Valid
30
Address Cycle Time
45
Address, FIFO_SEL Setup to nCS, nRD Valid
0
Address Stable to Data Valid
40
Address, FIFO_SEL Hold Time
0
Data Buffer Turn On Time
0
Data Buffer Turn Off Time
9
Data Output Hold Time
0
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note: A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and
de-asserted in any order.
Note: A[1] must toggle, fresh data is supplied each time A[1] toggles.
SMSC LAN9311/LAN9311i
451
DATASHEET
Revision 2.0 (02-14-13)