LAN9311 Datasheet, PDF (317/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
1846h
1847h
1848h
1849h
184Ah
184Bh
184Ch
184Dh
184Eh
184Fh
1850h
1851h
1852h
1853h-1854h
1855h
1856h
1857h
1858h
1859h
185Ah
185Bh-187Fh
1880h
1881h
1882h-1BFFh
SYMBOL
REGISTER NAME
SWE_PORT_MIRROR
Switch Engine Port Mirroring Register, Section 14.5.3.21
SWE_INGRESS_PORT_TYP Switch Engine Ingress Port Type Register, Section 14.5.3.22
SWE_BCST_THROT
Switch Engine Broadcast Throttling Register, Section 14.5.3.23
SWE_ADMT_N_MEMBER Switch Engine Admit Non Member Register, Section 14.5.3.24
SWE_INGRESS_RATE_CFG
SWE_INGRESS_RATE_CMD
Switch Engine Ingress Rate Configuration Register,
Section 14.5.3.25
Switch Engine Ingress Rate Command Register,
Section 14.5.3.26
SWE_INGRESS_RATE_CMD_STS
Switch Engine Ingress Rate Command Status Register,
Section 14.5.3.27
SWE_INGRESS_RATE_WR_DATA
SWE_INGRESS_RATE_RD_DATA
Switch Engine Ingress Rate Write Data Register,
Section 14.5.3.28
Switch Engine Ingress Rate Read Data Register,
Section 14.5.3.29
RESERVED
Reserved for Future Use
SWE_FILTERED_CNT_MII
SWE_FILTERED_CNT_1
Switch Engine Port 0 Ingress Filtered Count Register,
Section 14.5.3.30
Switch Engine Port 1 Ingress Filtered Count Register,
Section 14.5.3.31
SWE_FILTERED_CNT_2
Switch Engine Port 2 Ingress Filtered Count Register,
Section 14.5.3.32
RESERVED
Reserved for Future Use
SWE_INGRESS_REGEN_TBL_MII
Switch Engine Port 0 Ingress VLAN Priority Regeneration
Register, Section 14.5.3.33
SWE_INGRESS_REGEN_TBL_1
Switch Engine Port 1 Ingress VLAN Priority Regeneration
Register, Section 14.5.3.34
SWE_INGRESS_REGEN_TBL_2
Switch Engine Port 2 Ingress VLAN Priority Regeneration
Register, Section 14.5.3.35
SWE_LRN_DISCRD_CNT_MII
Switch Engine Port 0 Learn Discard Count Register,
Section 14.5.3.36
SWE_LRN_DISCRD_CNT_1
Switch Engine Port 1 Learn Discard Count Register,
Section 14.5.3.37
SWE_LRN_DISCRD_CNT_2
RESERVED
Switch Engine Port 2 Learn Discard Count Register,
Section 14.5.3.38
Reserved for Future Use
SWE_IMR
SWE_IPR
Switch Engine Interrupt Mask Register, Section 14.5.3.39
Switch Engine Interrupt Pending Register, Section 14.5.3.40
RESERVED
Reserved for Future Use
Buffer Manager (BM) CSRs
SMSC LAN9311/LAN9311i
317
DATASHEET
Revision 2.0 (02-14-13)