LAN9311 Datasheet, PDF (346/461 Pages) SMSC Corporation – Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
Register #:
Port0: 0440h
Port1: 0840h
Port2: 0C40h
Size:
32 bits
This read/write register configures the transmit packet parameters of the port.
BITS
31:8
7
6:2
1
0
DESCRIPTION
RESERVED
MAC Counter Test
When set, TX and RX counters that normally clear to 0 when read, will be
set to 7FFF_FFFCh when read with the exception of the Port x MAC
Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x), Port x
MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x),
and Port x MAC Receive Good Packet Length Count Register
(MAC_RX_GOODPKTLEN_CNT_x) counters which will be set to
7FFF_FF80h.
IFG Config
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config *4) + 12
Note: IFG Config values less than 15 are unsupported.
TX Pad Enable
When set, packets shorter than 64 bytes are padded with zeros if needed
and a FCS is appended. Packets that are 60 bytes or less will become 64
bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67
bytes respectively.
TX Enable
When set, the transmit port is enabled. When cleared, the transmit port is
disabled.
TYPE
RO
R/W
R/W
R/W
R/W
DEFAULT
-
0b
10101b
1b
1b
Revision 2.0 (02-14-13)
346
DATASHEET
SMSC LAN9311/LAN9311i