8101 Datasheet, PDF (99/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 4.3 Register Default Values (Cont.)
Register Register Address
Numbers (REGAD[7:0] Pins)
33–111
112–115
116–119
120–123
124–127
128–233
234–255
0b00011001–0b01101111
0b01110000–0b01110011
0b01110100–0b01110111
0b01111000–0b01111011
0b01111100–0b01111111
0b10000000–0b11101001
0b11101010–0b11111111
Register Name
Default
(Hex)
Reserved
Counter Half Full 1−4
0x0000
Reserved
Counter Half Full Mask 1–4
oxFFFF
Reserved
Counter 1-53 32-bit Management Counters 0x0000
Reserved
4.3 Register Definitions
The following paragraphs describe the 8101/8104 internal registers.
4.3.1 Register 0–MAC Address 1
15
0
A[47:32]
Note: A[47] 15-bit occurs on the REGD15 pin.
A[47:32]
MAC Address, First Word
[15:0], R/W
This is the fist of three words in the 48-bit MAC address.
The MAC address is used to receive unicast address
filtering of the DA, and serves as the SA for automatically
generated MAC control pause frames.
A0 (see Register 2) corresponds to the first bit
transmitted or received by the MAC section (DA[0] or
SA[0] in Figure 2.3).
Register Definitions
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