8101 Datasheet, PDF (62/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

When FCNTRL is deasserted and the MAC control AutoSend threshold
is not exceeded, one last autogenerated pause frame of pause_time = 0
is transmitted. To compensate for latency, the internal pause timer
internally shortens itself by 32 units from the value programmed in
“Register 20–Flow Control 2‚" Section 4.3.17.
Clearing the MCENDPS bit in “Register 19–Flow Control 1‚"
Section 4.3.16 programs the controller to eliminate the last
autogenerated pause frame with a pause_time = 0.
The structure of the autogenerated pause frame is described in
Figure 2.7.
Note:
The source address and pause_time parameter fields are
programmable through internal registers as shown in
Figure 2.7.
The FCNTRL pin and the MAC control AutoSend threshold can be
individually disabled, (they can be programmed to no longer initiate the
transmission of autogenerated pause frames). The FCNTRL pin is
enabled by default. Setting the FCNTRL_DIS bit in “Register 9–
Configuration 3‚" Section 4.3.10, disables the FCNTRL pin. The MAC
control AutoSend is disabled by default. Appropriately setting the MAC
control MCASND[3:0] bits in “Register 19–Flow Control 1‚"
Section 4.3.16, enables the MAC control AutoSend.
2.17.2 Transmitter Pause Disable
Receive pause frames normally pause the transmitter. Clearing the
MCNTRL bit in “Register 19–Flow Control 1‚" Section 4.3.16, programs
the controller to not pause the transmitter. When the MCNTRL bit is 0
received pause frames do not affect the transmitter.
2.17.3 Pass Through to FIFO
Receive pause frames are normally discarded and not passed to the
receive FIFO. Appropriately setting the MCPASS[1:0] bits in
“Register 19–Flow Control 1‚" Section 4.3.16, allows the receive pause
frames to be passed to the receive FIFO. These bits allow either all MAC
control frames, nonpause frames only, or pause frames only to be
passed to the receive FIFO.
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Functional Description
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