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| 8101 Datasheet, PDF (160/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller | |||
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Figure 6.11 Register Interface Timing, Counter Read Cycle (Between Different
Counters)
t87
REGCLK
t81
t82
t81
t82
REGCSn
REGWRn
t81
t82
REGRDn
t81
t82
REGAD[15:0]
Counter Address A
t84
t84
REGD[15:0] High-Z
16 Bits of
Not Valid Counter Results
t83
Note: No burst reading,
t81
t82
t81
t82
Counter Address B
t84
t84
Hi-Z
Not Valid
16 Bits of
Counter Results
High-Z
t83
6-16
Speciï¬cations
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