8101 Datasheet, PDF (89/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Chapter 4
Registers
The 8101/8104 controller has 136 internal 16-bit registers. Twenty-two
registers are available for setting configuration inputs and reading status
outputs. The remaining 114 registers are associated with the
management counters.
This chapter contains the following sections:
• Section 4.1, “Register Interface”
• Section 4.2, “Register Addresses”
• Section 4.3, “Register Definitions”
4.1 Register Interface
The register interface is a 16-bit bidirectional data interface that allows
access to the internal registers. The register interface consists of 29
signals:
• Sixteen bidirectional data I/O bits (REGD[15:0])
• Eight register address inputs (REGA[7:0])
• One chip select input (REGCSn)
• One clock input (REGCLK) The REGCLK clock frequency must be
between 5−40 MHz.
• One read select input (REGRDn)
• One write select input (REGWRn)
• One interrupt output (REGINT)
All register accesses are done on the rising edge of the REGCLK clock.
To access a register through the register interface, REGCSn must be
asserted and is sampled on the rising edge of REGCLK. On that same
8101/8104 Gigabit Ethernet Controller
4-1
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