8101 Datasheet, PDF (84/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

TXDC
TXENn
TXEOF
TXSOF
TXWM1n
TXWM2n
Transmit Packet Discard
Output
When TXDC is HIGH, the controller detects that current
packet being input on the system interface has an error,
rest of packet ignored. When LOW, The packet is not
discarded. TXDC is clocked out on thr rising edge of the
system clock.
If AutoClear mode is not enabled, this output is latched
HIGH and stays latched until cleared with the assertion
of the CLR_TXDC pin. If AutoClear mode is enabled, this
output is latched HIGH and automatically clears itself
LOW two clock cycles after TXEOF is asserted.
Transmit Enable
Input
This input must be low to enable the current data word
on TXD[31:0] to be clocked into the transmit FIFO.
TXENn is clocked in on the rising edge of the system
interface clock, SCLK.
Transmit End Of Frame
Input
This input must be asserted on the same clock cycle as
the last word of the packet is being clocked in on
TXD[31:0]. TXEOF is clocked into the device on the rising
edge of the system interface clock, SCLK.
Transmit Start Of Frame
Input
This input must be asserted on the same clock cycle as
the first word of the packet is being clocked in on
TXD[31:0]. TXSOF is clocked into the device on the rising
edge of the system interface clock, SCLK.
Transmit FIFO Watermark 1
Output
When TXWM1n is HIGH, the transmit FIFO data is less
than or equal to the transmit FIFO watermark 1. When
LOW, the transmit FIFO data is above the watermark.
TXWM1n is clocked out on the rising edge of the system
clock, SCLK.
Transmit FIFO Watermark 2
Output
When TXWM2n is HIGH, the transmit FIFO data is less
than or equal to the transmit FIFO watermark 2. When
LOW, the transmit FIFO data is above the watermark.
TXWM2n is clocked out on the rising edge of the system
clock, SCLK.
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Signal Descriptions
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