8101 Datasheet, PDF (41/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

The transmit watermark thresholds for TXWM1n and TXWM2n can be
programmed over the entire 4 Kbyte FIFO range. Each of the watermark
thresholds is independently programmed with five bits that reside in the
Transmit FIFO Threshold register. Whenever the data in the FIFO
exceeds the threshold of either watermark, the respective watermark pin
on TXWM1n or TXWM2n is asserted LOW. The watermark signals stay
asserted until the data in the FIFO goes below the respective thresholds.
2.9.3 TX Underflow
The transmit FIFO underflow condition occurs when the TX FIFO is
empty but the MAC is still requesting data to complete the transmission
of a packet. If the transmit FIFO underflows:
• Packet transmission to the 8B10B PCS is halted
• A /V/ code (see Table 2.8) is appended to the end of the partially
transmitted packet
• Any new data for the partially transmitted packet is discarded
Refer to Section 2.13, “Packet Discard” for more information about
discards.
2.9.4 TX Overflow
The transmit FIFO overflow condition occurs when the TX FIFO is full but
additional data is still being written into it from the system interface. If the
transmit FIFO overflows:
• The input to the TX FIFO is blocked and does not accept any more
data from the system interface until the TX FIFO space is freed up
• The data already stored in the TX FIFO for the partially loaded last
packet is transmitted with a /V/ code (see Table 2.8) appended to the
end of the packet to indicate an error
• Any new data for the partially loaded last packet is discarded
Refer to Section 2.13, “Packet Discard” for more information about
discards.
Transmit FIFO
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