8101 Datasheet, PDF (155/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 6.6 Transmit 10-Bit PHY Interface Timing Characteristics
Symbol Parameter
t61 TBC period
t62 TBC HIGH time
t63 TBC LOW time
TX[0:9] data valid before
t64 TBC rising edge
TX[0:9] data valid after
t65 TBC rising edge
TBC, TX[0:9]
t66 rise and fall time
Limit
Min
Typ
Max
7.992
8
8.008
3.2
4.8
3.2
4.8
2.0
1.0
Unit Conditions
ns
ns
ns
Assumes TBC duty
ns cycle = 40−60%
Assumes TBC duty
ns cycle = 40–60%
0.7
2.4
ns
Note: Refer to Figure 6.7 for timing diagram.
Figure 6.7 Transmit 10-Bit PHY Interface Timing
TBC
TX[0:9]
t₆₄
t₆₅
t₆₁
t₆₂
t₆₃
t₆₆
t₆₆
t₆₆
AC Electrical Characteristics
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