8101 Datasheet, PDF (13/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Figures
2.1 8101/8104 Block Diagram
2.2 Ethernet MAC Frame Format
2.3 Frame Formats and Bit Ordering
2.4 Little Endian vs. Big Endian Format
2.5 RXSOF/RXEOF Position
2.6 AutoNegotiation Data Format
2.7 Autogenerated Pause Frame Format
3.1 8101/8104 Interface Diagram
5.1 Gigabit Ethernet Switch Port Using the 8101/8104
5.2 Decoupling Recommendations
6.1 Input Clock Timing
6.2 Transmit System Interface Timing
6.3 Receive System Interface Timing
6.4 Receive System Interface RXABORT Timing
6.5 Receive System Interface RXOEn Timing
6.6 System Interface RXDC/TXDC Timing
6.7 Transmit 10-Bit PHY Interface Timing
6.8 Receive 10-Bit PHY Interface Timing
6.9 Register Interface Timing (Excluding Counter
Read Cycle)
6.10 Register Interface Timing, Counter Read Cycle
(of the Same Counter)
6.11 Register Interface Timing, Counter Read Cycle
(Between Different Counters)
6.12 8101 208-Pin PQFP Pinout
6.13 8104 208-Pin BGA Pinout
6.14 208-Pin PQFP Mechanical Drawing
6.15 208 mini-BGA (HG) Mechanical Drawing
2-3
2-4
2-5
2-9
2-13
2-39
2-45
3-2
5-2
5-17
6-4
6-6
6-8
6-9
6-9
6-10
6-11
6-12
6-14
6-15
6-16
6-17
6-19
6-21
6-22
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