8101 Datasheet, PDF (81/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

3.1 System Interface Signals
This section describes the 8101/8104 system interface signals.
CLR_RXDC
Clear RXDC
Input
When CLR_RXDC is asserted, the RXDC pin is cleared.
Wheh CLR_RXDC is LOW, the RXDC pin is not cleared.
CLR_RXDC is clocked in on the rising edge of the
system clock, SCLK.
This pin only clears RXDC when AutoClear mode is
disabled. When AutoClear mode is enabled, this pin is
ignored and RXDC is automatically cleared two clock
cycles after RXEOF is asserted.
CLR_TXDC
Clear TXDC
Input
When CLR_TXDC is HIGH, the TXDC pin is cleared.
When CLR_TXDC is LOW, the TXDC pin is not cleared.
TXDC is clocked in on the rising edge of the system
clock, SCLK.
This pin only clears TXDC when AutoClear mode is
disabled. When AutoClear mode is enabled, this pin is
ignored and TXDC is automatically cleared two clock
cycles after TXEOF is asserted.
FCNTRL
Flow Control Enable
Input
When FCNTRL is HIGH, transmitter automatically
transmits a MAC control pause frame. When FCNTRL is
LOW, the controller resumes normal operation. FCNTRL
is clocked in on the rising edge of the system clock,
SCLK.
RXABORT
Receive FIFO Data Abort
Input
When RXABORT is asserted, the packet being read out
on RXD[31:0] is aborted and discarded. When LOW, the
packet is not aborted and discarded. RXABORT is
clocked in on the rising edge of the system clock, SCLK.
RXBE[3:0]
Receive Byte Enable
Output
These outputs determine which bytes of the current data
on RXD[31:0] contain valid data. RXBE[3:0] is clocked
out of the device on the rising edge of the system
interface clock, SCLK.
System Interface Signals
3-3
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