8101 Datasheet, PDF (148/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 6.2 Input Clock Timing Characteristics
Symbol Parameter
t1 SCLK cycle time
t2 SCLK duty cycle
t3 TCLK period
t4 TCLK HIGH time
t5 TCLK LOW time
t6 TCLK to TBC delay
t7 REGCLK cycle time
t8 REGCLK duty cycle
Min
1/33
40
7.9992
3.6
3.6
0
1/5
40
Limit
Typ
8
Max
1/66
60
8.0008
4.4
4.4
8
1/40
60
Unit Conditions
1 MHz
%
ns
ns
ns
ns
1 MHz
%
Note: Refer to Figure 6.1 for timing diagram.
SCLK
TCLK
TBC
REGCLK
Figure 6.1 Input Clock Timing
t₁
t₂
t₂
t₃
t₆
t₄
t₅
t₇
t₈
t₈
System
Interface
10-Bit PHY
Interface
Register
Interface
6-4
Specifications
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