8101 Datasheet, PDF (8/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

2.8 Receive MAC
2.8.1 Preamble and SFD Stripping
2.8.2 CRC Stripping
2.8.3 Unicast Address Filter
2.8.4 Multicast Address Filter
2.8.5 Broadcast Address Filter
2.8.6 Reject or Accept All Packets
2.8.7 Frame Validity Checks
2.8.8 Maximum Packet Size
2.8.9 MAC Control Frame Check
2.9 Transmit FIFO
2.9.1 AutoSend
2.9.2 Watermarks
2.9.3 TX Underflow
2.9.4 TX Overflow
2.9.5 Link Down FIFO Flush
2.10 Receive FIFO
2.10.1 Watermarks
2.10.2 RX Overflow
2.10.3 RX Underflow
2.11 8B10B PCS
2.11.1 8B10B Encoder
2.11.2 8B10B Decoder
2.11.3 Start of Packet
2.11.4 End Of Packet
2.11.5 Idle
2.11.6 Receive Word Synchronization
2.11.7 AutoNegotiation
2.12 10-Bit PHY Interface
2.12.1 Data Format and Bit Order
2.12.2 Transmit
2.12.3 Receive
2.12.4 Lock To Reference
2.12.5 PHY Loopback
2.12.6 Signal Detect
2.12.7 TBC Disable
2.13 Packet Discard
2.13.1 Transmit Discards
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Contents
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
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