8101 Datasheet, PDF (154/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 6.5 System Interface RXDC/TXDC Timing Characteristics
Symbol Parameter
t51 TXDC/RXDC
assert delay time
t52 TXDC/RXDC
deassert delay time
t53 CLR_TXDC/RXDC
setup time
t54 CLR_TXDC/RXDC
hold time
TXDC/RXDC
rise and fall time
Limit
Min Typ
Max
0
8
Unit Conditions
ns
0
2 SCLK ns AutoClear mode off
cycle
+ 8 ns
0
3 SCLK ns AutoClear mode on
cycle
+ 8 ns
5
ns
0
ns
4
ns
Note: Refer to Figure 6.6 for timing diagram.
Figure 6.6 System Interface RXDC/TXDC Timing
SCLK
TXENn
RXENn
t₅₁
TXDC
RXDC
CLR_TXDC
CLR_RXDC
TXEOF
RXEOF
t₅₂
t₅₃
t₅₄
Autoclear
Mode
Off
Autoclear
Mode
Off
6-10
Specifications
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