8101 Datasheet, PDF (157/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 6.8 Register Interface Timing Characteristics
Limit
Symbol Parameter
Min Typ Max Unit Conditions
t81 REGCSn, REGWRn,
10
ns
REGRDn, REGA, REGD
setup time
t82 REGCSn, REGWRn,
1
ns
REGRDn, REGA, REGD
hold time
t83 REGCLK to REGD
active delay
10
ns Read cycle.
All registers except
Counter Registers 1–53
6
ns Read cycle. Counter
REGCLK
Registers 1–53, first 16
cycles +
bits of counter result
10 ns
3
ns Read cycle. Counter
REGCLK
Registers 1–53, second
cycles +
16 bits of counter result
10 ns
t84 REGCLK to REGD
0
3-state delay
10
ns
t85 REGCLK to REGINT
0
assert delay
20
ns
t86 REGCLK to REGINT
0
deassert delay
20
ns
t87 Deassertion time between 4
reads
REG-
CLK
Note: Refer to Figure 6.9 and Figure 6.10 for timing diagrams.
AC Electrical Characteristics
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